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Tools & shortcuts

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Place component

Rotation and mirror
Place at exact coordinates

Set properties before choosing a symbol. Click in the canvas, or use exact coordinates. Drawing updates directly; Undo reverses each action. R rotates · M mirrors · Esc cancels.

Project engineering workspace

Simulation workspace

Symbols and libraries

Physical product

Engineering tools

Electrical edit

Edit copper

Board points use integer micrometres; via position uses millimetres. Native validation checks the whole copper candidate. Valid edits apply directly with Undo; findings require review.

Route points and captured anchors

Route one net

Choose a net and sizes. Native search proposes copper across top and bottom layers while checking pads, existing copper, drills, board edges and RF keep-outs. Review the whole proposal before applying it with one Undo.

Bounded to 300,000 explored nodes per connection and 96 connections. If no route fits, change the explicit grid/sizes or placement. This checks geometry and connectivity; power, thermal and RF acceptance use separate captured reviews.

Copper zone / ground plane

Native conservative grid fill respects copper, drills, board edges and captured RF keep-outs. Floating islands are removed by default. This is geometry and connectivity; current capacity and thermal/RF behavior remain unverified.

3D model

A STEP body replaces the footprint's nominal box in the 3D view, the enclosure checks, courtyards and keepouts. Every placement of this footprint uses it. The model is turned about X, Y and Z, then offset, into the footprint frame: origin on the footprint origin, Z up from the mounting surface.

Supplier capability

Compares the routing rules, the captured fabrication profile and the drawn board with a supplier class. Raising the rules only tightens them and takes one Undo; nothing is rerouted.

CheckProjectSupplierResult

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Panel

Copies of this rectangular board on a grid. V-score boards abut and are scored along every boundary; mouse-bite boards sit in routed channels and hang on tabs with a row of small holes. Rails add handling edges, tooling holes and fiducials. The single-board package is unchanged.

Fabrication drawing

Overall dimensions from the lower-left datum, a drill table that matches the drill files, mounting-hole positions and stackup notes. It is a view of the current board: the fabrication package is unchanged.

Fiducial or test point

A fiducial is a bare copper dot without a net for assembly cameras; its ring stays free of all other copper and solder mask. A test point is an exposed round pad on one net, connected by ordinary copper. Neither gets solder paste.

Keepout

A keepout forbids copper (traces, pads and plane fill), vias or component bodies inside an area on the chosen sides. Touching the boundary counts as entering. Checks, plane fills, route search and via stitching all respect it.

Routing rules

Board values apply everywhere. Optional layer and net-class overrides resolve natively in the order class layer, class, board layer, board, and the same resolved rules drive copper checks, plane fills, route search and interactive routing. Default widths and via sizes prefill new copper; they are not checks. Changing rules re-checks existing copper, and findings require review.

Layer overrides (mm · blank inherits the board value)
LayerClearanceMin widthMax widthDefault width
Net classes
Differential pairs and length groups

A pair routes as two traces at the declared gap; its skew and uncoupled length are checked natively. A length group keeps its routed nets within the tolerance.

Current capacity

Declare the continuous load current of a net and the trace temperature rise you accept. Every trace of the net is rated natively for the whole current with the IPC-2221 design-chart fit for outer layers; planes, vias and IPC-2152 corrections are not included.

TraceNetWidthRiseMinimum width
Resolved rules per net (native)
NetClassTop clearance / min / maxBottom clearance / min / max

Stitch planes with vias

Native stitching places vias on the pitch lattice where the chosen net's delivered planes cover the whole via on both layers and the same clearance predicate as route search passes. Vias keep the explicit sizes; no partial set is proposed. Apply is one Undo. Plane copper is geometry and connectivity only; current, thermal and RF behavior stay unverified.

Board outline, cutouts and slots

The native board contour is the outline minus its cutouts; routed slots are drilled openings. Placements, copper, drills, zone fills and the enclosure are re-checked against the new contour and nothing is moved or rerouted. Apply is one Undo. Rounded corners become exact chords on the board grid; the manufacturer still owns routing tolerances.

Silkscreen text and lines

Silkscreen objects are board data shaped by the bundled native fonts; the same outlines go to the silk Gerbers and the manufacturing checks for stroke width, mask openings and the board edge. Objects bound to a footprint follow it when it moves, turns or flips. Apply is one Undo.

Bound objects are positioned in the footprint frame: x along its body, y up, before its turn and side. The native plan snaps coordinates to the grid.

PCBWay · Manufacturing review

Read back from the exported Gerber and drill files. Bottom uses the same top-view axes.
Manufacturing findings
Files in the PCBWay ZIP
FileLayerReadback
Assembly and process notes

Carry any captured via-in-pad filling/capping requirements into your PCBWay order; drill files alone do not specify that process.

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